The present invention relates to synchronizing clock pulses among layout blocks of an integrated circuit. More specifically, but without limitation thereto, the present invention relates to inserting a minimum set of delay cells between a clock driver and each circuit element to synchronize clock pulses in an integrated circuit.
An integrated circuit chip design typically includes a hierarchy of layout blocks, or hard macros (xe2x80x9chardmacsxe2x80x9d). These circuit elements generally require a common clock pulse to synchronize their operation with one another. Because the wire length between a clock pulse generator and each circuit varies, the propagation delays in the wiring also vary. The clock pulses arrive at each circuit element at a different time due to the propagation delays in the wiring. This variation in propagation time of the clock pulses to each of the circuit elements is called clock skew. In high speed circuits, clock skew of 100 picoseconds may cause a malfunction in the chip.
Current methods for correcting clock skew add compensating lengths of wire to balance the propagation delays. A disadvantage of these methods is that the increased wire length increases capacitive coupling to other circuits and adds loading capacitance that may distort the clock pulse waveform.
The present invention advantageously addresses the problems above as well as other problems by providing a method for synchronizing clock pulses for an integrated circuit by a balanced clock tree with delay cells.
In one embodiment, the present invention may be characterized as a method for synchronizing clock pulses for an integrated circuit that includes the steps of (a) finding a relative delay with respect to a clock signal for a plurality of circuit elements and (b) inserting a delay cell between the clock signal and each of the plurality of circuit elements for each of the plurality of circuit elements that has a relative delay greater than a minimum delay to minimize clock skew.